JUAN JOSE
RODRIGUEZ ANDINA
TITULAR DE UNIVERSIDADE - TEMPO COMPLETO
Universidade de Lisboa
Lisboa, PortugalPublicaciones en colaboración con investigadores/as de Universidade de Lisboa (13)
2013
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Design and validation of configurable online aging sensors in nanometer-scale FPGAs
IEEE Transactions on Nanotechnology, Vol. 12, Núm. 4, pp. 508-517
2012
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Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits
Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, Núm. 4, pp. 421-434
2011
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Lower V DD operation of FPGA-based digital circuits through delay modeling and time borrowing
Journal of Low Power Electronics, Vol. 7, Núm. 2, pp. 185-198
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Performance failure prediction using built-in delay sensors in FPGAs
Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
2010
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Impact of power supply voltage variations on FPGA-based digital systems performance
Journal of Low Power Electronics
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Investigating the use of BICS to detect resistive- open defects in SRAMs
Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010
2009
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Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies
2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
2008
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Process tolerant design using thermal and power-supply tolerance in pipeline based circuits
2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS
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Process tolerant design using thernal and power-supply tolerance in pipeline based circuits
Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
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Time Management for Low-Power Design of Digital Systems
Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 410-419
2007
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Improving tolerance to power-supply and temperature variations in synchronous circuits
Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
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On-line dynamic delay insertion to improve signal integrity in synchronous circuits
Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium
2006
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Dynamic fault detection in digital systems using dynamic voltage scaling and multi-temperature schemes
Proceedings - IOLTS 2006: 12th IEEE International On-Line Testing Symposium