Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento-ko ikertzaileekin lankidetzan egindako argitalpenak (15)

2011

  1. IP core to leverage RTOS-based embedded systems reliability to electromagnetic interference

    Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011

  2. Modeling the effect of process variations on the timing response of nanometer digital circuits

    LATW 2011 - 12th IEEE Latin-American Test Workshop

  3. Performance failure prediction using built-in delay sensors in FPGAs

    Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

  4. Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects

    LATW 2011 - 12th IEEE Latin-American Test Workshop

2010

  1. Delay modeling for power noise-aware design in Spartan-3A FPGAS

    6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

2009

  1. Measuring clock-signal modulation efficiency for systems-on-chip in electromagnetic interference environment

    2009 10th Latin American Test Workshop, LATW 2009

2008

  1. Delay modeling for power noise and temperature-aware design and test of digital systems

    Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 385-391

  2. Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits

    Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

  3. Process tolerant design using thermal and power-supply tolerance in pipeline based circuits

    2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS

  4. Robust solution for synchronous communication among multi clock domains

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

  5. Signal integrity enhancement in digital circuits

    IEEE Design and Test of Computers, Vol. 25, Núm. 5, pp. 452-461

  6. Time Management for Low-Power Design of Digital Systems

    Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 410-419

2007

  1. Enhancing the tolerance to power-supply instability in digital circuits

    Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

  2. Improving the tolerance of pipeline based circuits to power supply or temperature variations

    Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

2005

  1. Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test

    Proceedings - 11th IEEE International On-Line Testing Symposium, IOLTS 2005