JUAN JOSE
RODRIGUEZ ANDINA
TITULAR DE UNIVERSIDADE - TEMPO COMPLETO
Judit
Fernández Freijedo
Publicacions en què col·labora amb Judit Fernández Freijedo (20)
2013
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Aging monitoring with local sensors in FPGA-based designs
2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
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Design and validation of configurable online aging sensors in nanometer-scale FPGAs
IEEE Transactions on Nanotechnology, Vol. 12, Núm. 4, pp. 508-517
2012
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Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits
Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, Núm. 4, pp. 421-434
2011
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IP core to leverage RTOS-based embedded systems reliability to electromagnetic interference
Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
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Lower V DD operation of FPGA-based digital circuits through delay modeling and time borrowing
Journal of Low Power Electronics, Vol. 7, Núm. 2, pp. 185-198
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Modeling the effect of process variations on the timing response of nanometer digital circuits
LATW 2011 - 12th IEEE Latin-American Test Workshop
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Performance failure prediction using built-in delay sensors in FPGAs
Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
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Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects
LATW 2011 - 12th IEEE Latin-American Test Workshop
2010
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Delay modeling for power noise-aware design in Spartan-3A FPGAS
6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
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Impact of power supply voltage variations on FPGA-based digital systems performance
Journal of Low Power Electronics
2009
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Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies
2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
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Measuring clock-signal modulation efficiency for systems-on-chip in electromagnetic interference environment
2009 10th Latin American Test Workshop, LATW 2009
2008
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Delay modeling for power noise and temperature-aware design and test of digital systems
Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 385-391
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Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits
Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008
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Power-supply instability aware clock signal modulation for digital integrated circuits
IEEE International Symposium on Electromagnetic Compatibility
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Robust solution for synchronous communication among multi clock domains
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
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Time Management for Low-Power Design of Digital Systems
Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 410-419
2007
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Enhancing the tolerance to power-supply instability in digital circuits
Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures
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Improving tolerance to power-supply and temperature variations in synchronous circuits
Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
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On-line dynamic delay insertion to improve signal integrity in synchronous circuits
Proceedings - IOLTS 2007 13th IEEE International On-Line Testing Symposium