Publications en collaboration avec des chercheurs de Pontifícia Universidade Católica do Rio Grande do Sul (24)

2013

  1. Aging monitoring with local sensors in FPGA-based designs

    2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings

  2. Design and validation of configurable online aging sensors in nanometer-scale FPGAs

    IEEE Transactions on Nanotechnology, Vol. 12, Núm. 4, pp. 508-517

2012

  1. Modeling the effect of process, power-supply voltage and temperature variations on the timing response of nanometer digital circuits

    Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 28, Núm. 4, pp. 421-434

2011

  1. IP core to leverage RTOS-based embedded systems reliability to electromagnetic interference

    Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011

  2. Lower V DD operation of FPGA-based digital circuits through delay modeling and time borrowing

    Journal of Low Power Electronics, Vol. 7, Núm. 2, pp. 185-198

  3. Modeling the effect of process variations on the timing response of nanometer digital circuits

    LATW 2011 - 12th IEEE Latin-American Test Workshop

  4. Performance failure prediction using built-in delay sensors in FPGAs

    Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

  5. Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects

    LATW 2011 - 12th IEEE Latin-American Test Workshop

2010

  1. Delay modeling for power noise-aware design in Spartan-3A FPGAS

    6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

  2. Impact of power supply voltage variations on FPGA-based digital systems performance

    Journal of Low Power Electronics

  3. Investigating the use of BICS to detect resistive- open defects in SRAMs

    Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium, IOLTS 2010

2009

  1. Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies

    2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009

  2. Measuring clock-signal modulation efficiency for systems-on-chip in electromagnetic interference environment

    2009 10th Latin American Test Workshop, LATW 2009

2008

  1. Delay modeling for power noise and temperature-aware design and test of digital systems

    Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 385-391

  2. Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits

    Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

  3. Power-supply instability aware clock signal modulation for digital integrated circuits

    IEEE International Symposium on Electromagnetic Compatibility

  4. Process tolerant design using thermal and power-supply tolerance in pipeline based circuits

    2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS

  5. Process tolerant design using thernal and power-supply tolerance in pipeline based circuits

    Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

  6. Time Management for Low-Power Design of Digital Systems

    Journal of Low Power Electronics, Vol. 4, Núm. 3, pp. 410-419

2007

  1. Enhancing the tolerance to power-supply instability in digital circuits

    Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures